1. Field of Invention
The present invention relates generally to efficient buffer management in a computer system, and more specifically to automatically self-triggering the outbound processing of buffer contents.
2. Background of Invention
The speed and efficiency of an integrated circuit or computer program is affected by the efficiency of the processing of buffer output. Both hardware and software architectures frequently involve large numbers of buffers, to which various data are written during system operation. The contents of these buffers are then output to various destinations. Because of the large number of buffers potentially involved in a system, even relatively minor inefficiencies in output management can introduce substantial latency.
In the prior art, buffer output is typically managed by first writing data to a buffer, and then initiating a start operation to begin the output processing, once the buffer is full. This method works, but uses dedicated clock cycles to begin the output processing, thereby taking longer than would be desirable.
A prior art method designed to speed up such operations involves using direct memory access to write data to a destination, but this still introduces some latency in the form of the overhead involved in the direct memory access operation. Furthermore, using direct memory access adds a great deal of complexity. This is especially true where multiple processors are being used, in which case the coordination of the direct memory access and the processors becomes extremely complex, and thus prone to error.
What is needed are methods, computer systems and integrated circuits to efficiently manage buffer output without introducing unnecessary latency or involving the inherent complexity of direct memory access.